Intel is attracting significant interest from external customers through its advanced packaging solutions at Intel Foundry. The company’s newest packaging technologies are preparing to enter mass production starting next year.

Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology allows designers to optimize cost, power, and bandwidth at the system level. This technology provides high-density connectivity without the cost and space disadvantages of a full-size silicon interlayer.

Cost Advantage and Production Schedule with EMIB-T

The EMIB-T variant uses TSV technology to provide direct access to the power contacts of ASICs and offers multi-kilowatt solutions in a single package. According to PCB and silicon substrate manufacturer Unimicron, Intel’s EMIB-T technology will reach high-volume production in 2027.

ASIC designers such as Broadcom and Meta are valuing the transition from TSMC’s CoWoS packaging to EMIB in order to reduce costs and maintain sample advantages. The price difference between EMIB-T and CoWoS can reach up to 50% depending on the need for a valuable intermediate layer.

This cost advantage allows customers to invest in different areas of their manufacturing processes. Intel aims for customers to scale up silicon using all variants, including EMIB, EMIB-M, and EMIB-T.

TSMC’s packaging challenges and Intel’s strategy

Intel is trying to attract customers from TSMC with advanced packaging technologies. It is stated that TSMC is experiencing some issues with the CoWoS-L packaging used for NVIDIA’s Vera Rubin design.

In the Rubin Ultra design, a four-die architecture, it is claimed that the processor dies cannot make full contact with the substrate due to package bending. This is one of the challenges TSMC faced in its CoWoS-L design.

Intel aims to package multi-die structures supporting high-bandwidth memory more efficiently with EMIB technology. What kind of change do you think this competition will create in the semiconductor world?